The present invention addresses two fundamental problems limiting the utility of present-day microwave semiconductor devices: low operating voltage and low input and output impedance.
Essentially most microwave solid state amplifiers employ power Gallium Arsenide (GaAs) semiconductor devices as amplifying elements. The low breakdown voltage of these semiconductor devices limits their maximum operating voltage, usually to less than 10 V.
Moreover, in many amplifier designs, it is desirable to achieve relatively high output power over a wide bandwidth. However, because microwave power devices have an impedance of only a few ohms, which is small compared to the 50 Ohms (50 .OMEGA.) impedance in conventional systems, it is very difficult to match these devices to the 50 .OMEGA. system impedance over a wide bandwidth without substantial degradation in performance. Furthermore, where the device in question is battery-powered, such as a cordless telephone or the like, limitations imposed by current battery technology typically limit the available voltage to 3 V. As the devices also have limited current-carrying ability, these voltage limitations effectively limit the output power available.
In order to obtain efficient transfer of power from a microwave device to an associated output load, the output impedance of the device must be matched to the impedance of the load. This is particularly a challenging problem in microwave links and satellite transmission systems, where the output impedance of the device must be matched to the transmission line impedance, which is usually 50 .OMEGA.. Note that the output impedance of a typical power GaAs MESFET device, providing 3 watts output power, is around 5 .OMEGA.. This mismatch requires costly and inefficient impedance matching networks, and limits the device to narrow band performance. The combination of low operating voltage and low output impedance has limited the effective output power of these devices. The same is true to a greater or lesser degree in amplifiers using other types of semiconductors, such as Gallium Arsenide (GaAs) or Indium Phosphide (InP) HEMT, PHEMT and HBT devices, as well as silicon bipolar or MOSFET devices.
The prior art has attempted to overcome the inherent power limitation of individual power semiconductor elements by providing multiple devices connected in parallel, resulting in extremely small impedance levels. However, matching circuits using traditional parallel power combining circuits are complex, lossy, and do not provide an efficient solution to the impedance mismatch problem noted above.
More specifically, FIG. 1 shows a conventional high voltage, multiple-element FET amplifier circuit, for microwave communication and satellite transmitters. The circuit shown is described in detail in Ezzeddine et al, "High-Voltage FET Amplifiers for Satellite and Phased-Array Applications", IEEE MTT-S Int. Microwave Sym. Digest, pp. 336-9 (1985). In this circuit, the input signal to be amplified is supplied at terminal 10, as indicated by the legend "RF in". The input signal is divided by a power divider network 12, and supplied to four identical input matching networks 14. The input signal is then fed to the gate terminals G of four identical field-effect transistors (FETs) 16. The output signals from all four FETs are combined by a power combiner 22. This circuit, where the DC supply voltage is provided in series configuration, and the RF signal is combined in parallel configuration, requires both an input power divider and an output power combiner; these components not only increase the size and weight of the amplifier but also degrade the amplifier performance because of the loss in the power divider and combiner circuits.
In a typical satellite transmitter a 24-40V bus is available for the DC bias voltage V.sub.dd, that is, to provide a supply voltage to the transistor devices 16 to provide power amplification. However due to the low transistor breakdown voltage, the bias voltage is limited by to a maximum between 6 and 10 V; that is, the voltage V.sub.ds across the drain terminal D and the source terminal S cannot exceed this value. Therefore, the input voltage V.sub.dd is divided by a string of four series-connected resistors 18 so that each transistor 16 "sees" only 6-10 V (i.e., V.sub.dd /4) as V.sub.ds across its drain and source terminals; the values indicated on FIG. 1 next to the drain terminals of each transistor (e.g., 3 V.sub.ds) are referenced to ground. It will be appreciated by those of skill in the art that in this circuit configuration, the input voltage V.sub.dd, having been divided by resistors 18 to a value suitable as DC bias voltage V.sub.ds, is effectively provided in series across the four transistors 16.
As noted, the input RF signal is divided by power divider 12 and supplied, by way of input matching networks 14, to each of four transistors 16 for separate amplification. The amplified RF signal provided by each transistor 16 is supplied to an output matching network 20, and their output signals are combined in a power combiner 22, becoming the "RF out" signal at terminal 24. The input RF signal is thus divided and amplified in parallel; the amplified signals are recombined by the power combiner 22, forming the RF out signal.
It will be appreciated that a choke 26 is provided between the terminal 30 to which V.sub.dd is applied and the drain terminal of the first transistor 16; the choke 26 allows the DC bias current to flow, while blocking flow of the RF input signal. Correspondingly, capacitors 28 are provided between the points at which adjacent pairs of transistors are connected and ground, grounding any RF energy that might otherwise flow between adjacent transistors 16, but preventing flow of the bias current to ground. The effect of capacitors 28 is therefore to provide RF isolation of the four transistors 16 from one another, so that the divided input signal is separately amplified by each of the transistors, that is, is amplified in parallel.
The prior art circuit of FIG. 1 can thus be characterized as providing series connection of the DC bias voltage and parallel connection of the RF signal. As noted, while this circuit has been successful commercially, it includes complex and inefficient RF power dividing and combining components. Further, each of the parallel amplifying "cells" requires input and output matching networks; in essence, the function of the output matching networks 20 and the power combiner 22 is to match the low output impedances of the transistors 16, typically 5-10 .OMEGA., to the desired impedance of an antenna or another output device, typically 50 .OMEGA.. As will be appreciated by those of skill in the art, such components are costly, inefficient and due to complexity result in good performance only over a narrow bandwidth.